Differential digital signals are used for carrying digital data coded as a difference voltage between a pair of conductors. This data format has the advantage of being more immune to noise and cross talk than are single ended signals. The noise immunity is based on impedance balance and common mode rejection. For properly designed conductor pairs, noise and cross talk impact the two branches of a differential pair in a similar fashion. Impact on the differential signal component is limited. This first order noise suppression can be maintained also when connecting transmitters and receivers to the differential line, given that their impedances are well balanced.
In order to exploit this means for noise suppression, a differential line receiver must be able to interpret solely the differential signal component, while essentially ignoring common mode signal components. The range of common mode voltages where a receiver has this capability is called the common mode range.
The common mode signal components a differential receiver is subjected to are often dominated by a DC offset. In most cases, this is different from the optimum common mode level for the receiver. On top of the DC offset is a whole spectrum of unwanted common mode signals originating from cross talk and ground currents creating offset voltages between transmitter and receiver grounds. Longer lines are subjected to more common mode noise. For well designed longer transmission lines, however, the common mode noise is low pass filtered much more than the differential signal component. Therefore it would be desirable to high-pass filter the input signal before entering the differential receiver. For ordinary base band data however, this cannot be done since the differential and common mode spectra overlap. As an example, for NRZ coded data the differential spectrum goes all the way down to DC.
EP 0840442 A1 and U.S. Pat. No. 4,714,895 are examples of differential amplifiers having a switched capacitor network to detect the common mode signal at the amplifier output, the output value of the switched capacitor network being fed back to the amplifier to enable compensation. Differential input amplifiers with differential outputs are used. These amplifiers have differential feedback networks determining the main properties of the filter. Since all signal processing is purely differential, the common mode level is a don""t care. Any common mode voltage where the amplifiers can process the differential signals will satisfy the differential feedback network.
Common mode control is provided to ensure that the amplifier operates within the limits imposed by the power supply. This is often referred to as xe2x80x9ccommon mode feedbackxe2x80x9d for differential output amplifiers. The Common mode feedback network senses the common mode level of the amplifier output and modulates the biasing of the amplifier to keep the common mode voltage within bounds.
Although the common mode level of a differential signal is controlled, the known common mode feedback technique cannot be used for adjusting the input common mode level to an amplifying element. The known common mode feedback network adjusts the output common mode level from a linear amplifier to avoid clipping in that amplifier.
Among the objects of this invention is the circumvention of the drawbacks of the prior art discussed above. In particular, the purpose of this invention is to create a differential transfer circuit that can operate under optimum conditions with input signals having a wider range of common mode voltages and/or currents.
According to the present invention, the input to a differential receiver is first passed through a differential transfer circuit, which substantially removes the common mode component of the differential signal by means of controlling the charge on capacitors coupled between each of the differential transfer circuit inputs and each of the differential receiver inputs respectively, dependent on the common mode level of the signal.
Preferably, this is done using switched capacitor circuitry.
Preferably, one switched capacitor circuit is provided for each of the capacitors coupled between each of the differential transfer circuit inputs and each of the differential receiver inputs.
Preferably, each switched capacitor circuit comprises a further capacitor, a first and second switching device, which are switched in an in phase manner by said clock circuit so as to alternately connect, in a first stage of said clock""s cycle to connect said switched capacitor across the output signal of an input common mode level detection device, representing the common mode level on the incoming signal, and a reference level, and in a second stage of said clock""s cycle said further capacitor in parallel with the first or second capacitor with which said charge control circuit is associated.
Preferably the reference level is the same for each switched capacitor circuit. Different reference levels may be provided if the generation of a differential DC offset across the output terminals of the differential signal transfer circuit is desired, e.g. for compensating the amplifier receiving the output signals from the differential transfer circuit.
The switching of the switched capacitor circuits may be controlled by a common clock, or a separate clock may be provided for each switched capacitor circuit.
Where separate clocks are provided for each switched capacitor circuit, the clocks may, or may not oscillate at the same frequency.
Where separate clocks are provided for each switched capacitor circuit, and do oscillate at the same frequency, they may, or may not be in phase with one another,
Preferably the frequency of the cycle of the clock circuits is higher than twice the highest frequency in the common mode voltage spectrum at an appreciable power level, for example 20 dB below the differential signal power, at the input of the differential transfer circuit.
Preferably the switching devices are implemented using transistor transmission gates.
Preferably the input common mode is detected using a first and a second resistive element coupled in series across the first and second input lines so as to form a potential divider arrangement, the voltage between the two resistors being representative of the common mode value of the input signal.
Preferably, the common mode component of a differential signal Vin is processed without using amplifying elements. This makes it possible to operate on the input signal to a digital signal receiver or to a linear amplifier (6) for the purpose of making the input signal common mode variations that the receiver is subjected to much less than the common mode variations of the input signal Vin to the differential signal transfer circuit.